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vtracer - Verilog Testbench auxiliary tool

VCD is a standard signal trace format for HDL simulations. Often, users must compare behaviors of 2 different models which are supposed to work similarly. For example, when a Verilog core design is modified, users must verify that output pins of both the original and modified cores, behave the same if given the same stimulus. But the testbenches for each model are different, and therefore the behavors are slightly different also.

The 'VTracer' package includes a set of configurable Perl scripts which performs comparison between pairs of signals from 2 different VCD files, and a sample Testbench demonstrating the integration of the tool.

Obtaining

Web pagehttp://sourceforge.net/projects/vtracer/
Source tarball http://prdownloads.sourceforge.net/vtracer/vtracer.tar.gz?download
Source informationhttp://sourceforge.net/project/showfiles.php?group_id=111719
Version 1.0 (stable) released on 2004-06-13
Licensed under The GNU General Public License, Version 2.
This is not a GNU package.

Support contacts

Help List<DNaiger@bigfoot.com>
Developer List<DNaiger@bigfoot.com>
Bug List<DNaiger@bigfoot.com>

Project contacts

Maintainers
Developers

Related information

Source repository:pserver:anonymous@cvs.sourceforge.net:/cvsroot/vtracer http://sourceforge.net/cvs/?group_id=111719
InterfacesX Window System
Source languagesPerl, Verilog

Entry information

License verified byJanet Casey <jcasey@gnu.org> on 2004-06-17
Entry compiled byJanet Casey <jcasey@gnu.org>

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